Principal DFT Engineer
Core
Define and own DFT architecture for complex SoCs, lead implementation and verification across the full lifecycle, and drive DFT strategy to ensure high test quality and manufactability for next-generation AI connectivity chips.
Role type
Principal DFT Engineer (Strategic R&D Lead)
Builds
Complex semiconductor chips for AI infrastructure (CXL, Ethernet, NVLink, PCIe, UALink)
Domain
Semiconductor / AI Infrastructure / High-Speed Connectivity
Deliverable
production ML models | product features
Required skills
DFT architecture (Scan, MBIST, LBIST, JTAG/iJTAG, ATPG), DFT implementation and verification, DFT strategy definition, cross-functional technical leadership, DFT flow optimization, scripting (Tcl, Python, Perl), DFT tool expertise (Siemens Tessent, Synopsys TestMAX)
Preferred skills
Advanced process nodes (7nm and below), high-speed connectivity design experience, hierarchical DFT methodologies, chiplet-based system design, silicon bring-up and yield optimization
Technologies
CXL, Ethernet, NVLink, PCIe, UALink, Siemens Tessent, Synopsys TestMAX
Responsibilities
Define DFT architecture and strategies for complex SoCs; Lead DFT planning, specification, and quality tracking; Drive DFT implementation, integration, and verification at block, full-chip, and chiplet levels; Develop scalable DFT methodologies and automation frameworks; Collaborate with RTL, Physical Design, and Test teams; Optimize DFT integration to improve quality, PPA, and turnaround time
Seniority
Principal, hands-on IC with strategic leadership
