ASIC Physical Design
2,686 open positions
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Non-Volatile Memory (NVM) Architect ON SemiconductorBrno, South Moravia, Czech Republic 3mo Lead the definition, architecture, and development of next-generation embedded memory IP solutions for automotive, industrial, AI, and mixed-signal SoCs.
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Senior Physical Design Engineer MediaTekAustin, TX 3mo Drive Advanced Place & Route (APR) and physical verification (PV) signoff for high-performance CPU cores in 3nm and other leading-edge technology nodes.
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SOC Clock Distribution Engineer NVIDIAIsrael, Tel Aviv 3mo Designing and implementing SOC level clock requirements, including partitioning, CDC, trial synthesis, and design quality checks for complex networking chips.
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Hardware Engineer (Switch/Cloud Gateway) UbiquitiTaipei 3mo Design next-generation Ethernet hardware including Cloud Gateways, Gateway Routers, and Switches.
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Principal SOC Physical Verification & Integration Specialist Enchargeai36India 3mo Drive physical assembly and signoff of next-generation SOCs from floorplan to tapeout, ensuring seamless integration of massive multi-hierarchical blocks.
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Functional Safety Architect AlteraSan Jose, California, United States $149k3mo Lead functional safety activities and device safety architecture for next-generation semiconductor devices across Avionics, Space, Defense, Automotive, and Industrial markets.
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GPU Physical Design Engineer, STA/Timing AppleAustin, United States of America 3mo Design and manufacture high-performance, power-efficient processors by ensuring timing closure for complex GPU designs.
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Principal SoC Architect (f/m/div) InfineonMunich 3mo Define requirements and specifications for System-on-Chip (SoC) architectures, integrating standard IP blocks and developing digital power control algorithms using AI-driven methodologies.
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Design Implementation Synthesis Engineer, Staff / Sr Staff QualcommBangalore, India 3mo Staff/Sr Staff engineer responsible for physical synthesis, timing closure, and low-power design implementation for hardware chips.
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IC Design Engineer SilabsSingapore 3mo Designing digital circuits and integrating them into System-on-Chip (SoC) infrastructure for low-power wireless connectivity solutions.
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Sr Engineer - Physical Design SiFiveBengaluru, Karnataka, India 3mo Senior Physical Design Engineer responsible for end-to-end RTL-to-GDS implementation of next-generation IPs, optimizing Power, Performance, and Area (PPA) at the convergence of microarchitecture and physical layout.
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Staff Digital Design Engineer Renesas-ElectronicsChandler, Arizona, us 3mo Architecting, designing, and integrating low-power digital circuits for mixed-signal data conversion and power management products in advanced process nodes.
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Principal Hardware Engineer, AI Systems MicrosoftUnited States, Washington, Redmond 3mo End-to-end technical owner for next-generation AI and GPU platforms from architecture handoff through production deployment and fleet readiness.
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Sr. Staff Physical Design Timing Engineer (STA) LightmatterMountain View, CA CA$191k3mo Drive backend digital execution and timing closure for leading-edge silicon photonics chips in extreme-scale data centers.
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Principal Hardware ASIC Architect engineer NxpHyderabad 3mo Define and own architecture for compute, memory, interconnect, and high-speed interface subsystems in AI inference chips, balancing performance, power, and area (PPA) from concept through silicon.
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Design Engineer II CadenceHYDERABAD 3mo Developing, automating, and maintaining EDA flows and scripts for physical implementation of IP cores and soft controllers to optimize performance and power.
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ASIC Implementation Engineer PD BroadcomUSA-CA San Jose Innovation Drive $122k3mo ASIC top level floorplan Physical Design Engineer responsible for taking RTL to silicon tape-out for AI and PCIe Switch products.
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Principal High-Speed I/O Architect (PCIe, CXL, UA Link) ArmAustin, Texas $250k3mo Design and define innovative on-chip interconnect architectures (coherent and non-coherent) for scalable SoC platforms across mobile, automotive, datacenter, networking, and IoT markets.
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Engineer, Firmware Design MicronHyderabad - Phoenix Aquila, India 3mo Design and validation of on-chip controller and mixed signal circuitry in NAND FLASH chips.
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Senior Engineer, Digital Design Engineer AnalogdevicesUS, MA, Wilmington $117k3mo Lead methodology improvements for physical design flows across complex chip and SoC programs to enhance scalability, reuse, efficiency, and predictability.
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Digital IC Design Engineer (INT TRX) Texas InstrumentsDallas, TX, United States 3mo Architect and design high-performance digital circuits interfacing with analog systems for automotive and industrial applications.
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Principal ASIC Architect TensordyneRemote 3mo Lead architectural planning and definition of next-generation ASIC processors for generative AI inference acceleration, including specialized compute cores, embedded memory, RISC-V CPUs, and high-speed interconnects.
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Sr Staff Engineer, SoC RTL Design TenstorrentBoston 3mo Define, build, and optimize high-performance IP and SoC architectures for next-gen AI and compute workloads.
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