SoC Clocks Design Automation Engineer
Core
Developing and supporting clock-related design flows and methodologies for SoC and networking chips, ensuring efficient and high-quality design implementation.
Role type
SoC Clocks Design Automation Engineer
Builds
SoC top-level automation scripts and flows
Domain
Semiconductor physical design / Networking Silicon
Required skills
SoC design automation, Python scripting, physical design concepts (placement, routing, timing closure, ECO), EDA tools (Synopsys, Cadence), timing/power/noise analysis
Preferred skills
Perl/Tcl/Make scripting, timing-related analysis (crosstalk, noise, delay), power/timing optimization techniques
Technologies
Python, Perl, Tcl, Make, Synopsys, Cadence
Responsibilities
Develop and maintain design automation and methodologies for SoC and networking clock flows; Collaborate with design, STA, and project teams to ensure timely and high-quality design closure; Develop and improve SoC top-level automation scripts and flows; Support SoC integration and construction flow activities; Assist in timing, power, and noise analysis
Seniority
Mid-level, hands-on IC
