Design Implementation Synthesis Engineer, Staff / Sr Staff
Core
Staff/Sr Staff engineer responsible for physical synthesis, timing closure, and low-power design implementation for hardware chips.
Role type
Staff/Sr Staff IC Physical Synthesis Engineer
Builds
High-performance, low-power integrated circuits and netlists
Domain
Semiconductor hardware design / Digital Logic Synthesis
Required skills
Physical Synthesis, Timing Closure, Multi-clock domain design, MCMM, UPF (low-power), Perl/Python/TCL scripting, ECOs, Formal Verification
Technologies
Synopsys Design Compiler, Cadence Genus, UPF, Perl, Python, TCL
Responsibilities
Write timing constraints for synthesis and STA; Optimize multi-clock domain designs; Implement low-power techniques like clock gating; Collaborate with DFT and PD teams for netlist delivery; Handle ECOs and maintain quality matrices
Seniority
Staff/Sr Staff, hands-on IC
