Principal SOC Physical Verification & Integration Specialist
Core
Drive physical assembly and signoff of next-generation SOCs from floorplan to tapeout, ensuring seamless integration of massive multi-hierarchical blocks.
Role type
Principal SOC Physical Verification & Integration Specialist
Builds
Very large-scale SOCs (multi-billion transistor designs) for edge-to-cloud computing
Domain
Semiconductor design / AI hardware / Advanced process nodes (5nm, 3nm)
Deliverable
production ML models
Required skills
Top-level physical integration, hierarchical physical verification flows, full-chip DRC/LVS/ERC/Antenna/ESD/Latch-up signoff, cross-functional collaboration with PD/STA teams, design rule co-optimization with foundries, automation and flow development scripting
Preferred skills
Multi-die integration, 2.5D/3D packaging, chiplet-based architectures, leading tapeout operations in fast-paced environments, custom layout integration, mixed-signal IP drop-in
Technologies
Cadence Innovus, Siemens Calibre nmDRC/nLVS/PERC, Synopsys IC Validator
Responsibilities
Manage top-level floorplanning, bump planning, global power grid integration, and clock/routing integration; Architect and deploy hierarchical physical verification flows; Own full-chip signoff and debugging; Resolve integration conflicts between physical design and timing; Interpret complex foundry design rules; Develop scripts for automation and database manipulation
Seniority
Principal, hands-on IC
