Sr Engineer - Physical Design
Core
Senior Physical Design Engineer responsible for end-to-end RTL-to-GDS implementation of next-generation IPs, optimizing Power, Performance, and Area (PPA) at the convergence of microarchitecture and physical layout.
Role type
Senior IC Physical Design Engineer
Builds
Next-generation IP blocks (CPUs, high-speed interconnects, cache/memory hierarchies, specialized accelerators) for RISC-V compute platforms
Domain
Semiconductor chip design / Hardware architecture
Required skills
End-to-end physical design flow (Synthesis, Floorplanning, P&R, Signoff), RTL-to-GDS implementation, PPA optimization, EDA tool proficiency (Synopsys Fusion Compiler/PrimeTime, Cadence Innovus/Tempus), microarchitecture understanding, complex timing and routing debugging
Preferred skills
Experience on 7nm and below process nodes, expertise in specific IP domains (CPUs, fabrics, memory), mentoring junior engineers
Technologies
Synopsys Fusion Compiler, Synopsys PrimeTime, Cadence Innovus, Cadence Tempus
Responsibilities
Execute complete physical design flow for major sub-systems and IP blocks, partner with RTL/Architecture teams for co-optimization, apply advanced techniques for specific design classes (power efficiency, reliability, bandwidth), debug complex physical design challenges
Seniority
Senior, hands-on IC
