ASIC Physical Design
2,686 open positions
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) SpaceXAustin - 800 $175k4mo Developing cutting-edge next-generation silicon for deployment in space and ground infrastructures to enable global connectivity via the Starlink network.
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Principal SoC I/O Performance Architect Advanced Micro Devices, IncVANCOUVER, Canada 4mo Define and optimize I/O performance (bandwidth, latency, QoS) for next-generation SoCs using modeling, simulation, emulation, and post-silicon analysis to steer architecture decisions.
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Senior Performance Architect MicrosoftUnited States, Oregon, Hillsboro 4mo Develop performance modeling methodologies and analysis tools for System on Chip (SOC) and Intellectual Property (IP) to identify bottlenecks and justify architectural changes.
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Spécialiste FPGA - Aéronautique (F/H) AltenBordeaux, Nouvelle-Aquitaine, fr 4mo Develop and validate complex FPGA/SOC designs for critical embedded aerospace applications (video systems, flight computers, energy management) ensuring reliability and DO254 compliance.
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SoC Physical Design Engineer - Power Delivery AppleSan Jose, United States of America 4mo Develops and automates physical design flows for SoC power delivery, ensuring robust power grids from netlist to tapeout.
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Senior ASIC Timing Engineer NVIDIAUS, MA, Westford $168k4mo Drive physical design and timing closure for high-frequency, low-power DPUs, SoCs, and chiplets at block, sub-chip, and full-chip levels.
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Senior Physical Design Engineer Cisco2 Locations 4mo Lead backend VLSI design flow development from RTL to GDS, handling definition, physical synthesis, place and route, optimization, timing closure, and floor planning for high-quality ASIC designs.
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Staff Engineer, Physical Design SiFiveBengaluru, Karnataka, India 4mo Drive physical design implementation, timing closure, and structural backbone for next-generation RISC-V processor designs, focusing on global signal planning and high-performance interconnects.
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Principal Engineer, Digital Design (IO Subsystem) ON SemiconductorAllen, TX, United States 4mo Architecting and delivering a highly configurable IO subsystem for onsemi's microcontroller platform to enable scalability and product differentiation.
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ASIC SoC System Architect, Lund AxisSweden - Lund 4mo Define system-level architecture and requirements for ARTPEC SoC chips, selecting third-party IPs and collaborating with RTL design, verification, and ASIC vendor teams to deliver security features for IoT ecosystems.
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Baseband Design Engineer, Senior QualcommHsinchu City, Taiwan 4mo Senior hardware engineer responsible for Qualcomm chipset design, focusing on the MSM and peripheral sections, including board/device level solution evaluation and schematic design.
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Silicon Physical Design Engineer GraphcoreBristol 4mo Developing high-performance, power-efficient silicon layouts for next-generation AI superchips at leading-edge process nodes.
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Micro-Architect Quantum MachinesTel Aviv-Yafo, Israel 4mo Define and develop micro-architecture for complex logic blocks, driving architectural trade-off analysis and optimizing for performance and area.
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Senior Hardware Design Engineer, Ethernet Switching Arista-NetworksRoseville, CA, us $162k4mo Designing high-speed Ethernet switching hardware for AI clusters, data centers, and enterprise campuses.
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Principal Digital Design Engineer NxpBangalore 4mo Design, develop, and optimize digital logic circuits and systems for semiconductor, FPGA, or ASIC-based products across the full design cycle.
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Principal Digital Design Engineer Renesas-ElectronicsRemote 4mo Architect and design RTL in Verilog for mixed-signal integrated circuits, specifically digital sections of leading-edge memory data buffer chips for DDR5/DDR6.
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Technical Leader Physical Design
AmazonTel Aviv-Yafo, Tel Aviv, Israel
4mo
Leading physical design development for advanced semiconductor nodes, optimizing power, area, and performance for cloud computing infrastructure.
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Career Accelerator Program - Digital Design Engineer Texas InstrumentsTucson, AZ, United States 4mo Architect new TI products by defining, designing, modeling, and verifying digital circuits including 64-bit DSP processors, MMUs, and multicore shared memory systems.
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High Speed Interface Protocols, Principal AE CadenceSAN JOSE $123k4mo Architect high-speed interface solutions for customers using Cadence Serdes IP and showcase performance to win business opportunities.
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FPGA Development Engineer Hpe6 Locations 4mo Designing and delivering high-quality FPGA design and verification environments for networking hardware.
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Senior Staff Engineer Design InfineonBangalore BTP (India) 4mo Implement highly complex automotive SoC designs covering all aspects of Physical Design, from RTL2GDS flow to tapeout.
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Logic Lead FlirIndia - Pune 4mo Architectural design and FPGA implementation of next-generation wireless protocol analyzers to capture, demodulate, and process high-speed RF signals.
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Design Engineer LumilensSan Jose 4mo Design and implement digital front-end RTL blocks, including high-speed datapaths for UCIe and optical front-end interfaces.
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Physical Design Engineer
AmazonTel Aviv-Yafo, Tel Aviv, Israel
4mo
Developing semiconductor platforms and next-generation cloud products using revolutionary system architectures.
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Architecture ASIC Engineer MarvellCordoba, Argentina 4mo Design, simulate, and validate DSP ASICs for coherent optical communications systems serving Data Center interconnect and Long Haul/Metro markets.
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Product Engineer Siemens-EdaNew Cairo, EGY, Egypt $24k4mo Support the definition, promotion, and deployment of hardware-assisted acceleration using Veloce proFPGA CS prototyping solutions for semiconductor and systems customers.
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Senior Member of the Technical Staff GlobalFoundriesHsinchu 4mo Senior technical leadership role driving the development and delivery of high-performance compute processor IP solutions.
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SoC Architect ArmMultiple locations $309k4mo Architecting and designing high-volume, sophisticated System-on-Chip (SoC) platforms on groundbreaking nodes across mobile, automotive, datacenter, networking, and IoT market segments.
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