SOC Clock Distribution Engineer
Core
Designing and implementing SOC level clock requirements, including partitioning, CDC, trial synthesis, and design quality checks for complex networking chips.
Role type
Senior IC physical design engineer (clock distribution)
Builds
Complex networking chips and SOC designs
Domain
Semiconductor / Chip design
Required skills
SOC design, clock distribution, physical design, partitioning, CDC, trial synthesis, design quality checks, scripting (Perl, Python, Bash, Tcl)
Preferred skills
Experience delivering back to RTL, physical design readiness, resolving design quality issues
Technologies
Perl, Python, Bash, Tcl
Responsibilities
Designing and implementing SOC level clock requirements; Performing chip level design tasks including partitioning, CDC, trial synthesis, and design quality checks; Addressing functional and structural challenges including functional debug and physical design readiness
Seniority
Senior, hands-on IC
