Synthesis Engineer, Lead/Staff/Sr Staff
Core
Lead a high-performing team of engineers in the implementation domain for the Display Sub-System, focusing on physical synthesis, timing closure, and low-power design optimization for cutting-edge mobile products.
Role type
Senior/Staff/Lead IC Physical Design Synthesis Engineer
Builds
High-performance, low-power digital circuits and display subsystems for Qualcomm mobile SoCs
Domain
Semiconductor / Hardware Engineering / Physical Design
Required skills
Physical Synthesis, Timing Closure, Low-Power Design (UPF), RTL Lint, DFT, Scripting (Perl/Python/TCL), Multi-clock domain design, ECOs, Formal Verification
Preferred skills
RTL development, Physical Design, Synopsys DCG/Genus/Fusion Compiler, Cadence Conformal LEC/UPF
Technologies
Synopsys DCG, Genus, Fusion Compiler, Prime Time, Cadence Conformal LEC, UPF, TCL, Perl, Python
Responsibilities
Lead team execution for Display Sub-System; Develop signoff-quality and power intent constraints; Run RTL Lint, CLP, MEMBIST, DFT DRC; Develop TCL scripts for debugging and analysis; Perform timing closure and optimization for multi-clock domain designs; Handle ECOs and formal verification.
Seniority
Senior/Staff/Lead, hands-on IC with team leadership
