NoC (RTL) Design-Sr Lead/Staff/Sr Staff
Core
Definition, design, and verification of next-generation Network-on-Chip (NoC) and interconnect fabrics for Qualcomm SoCs powering smartphones, notebooks, smart glasses, automobiles, and servers.
Role type
Sr. Lead/Staff NoC (RTL) Design Engineer
Builds
Coherent and non-coherent interconnect fabrics and related IPs for Qualcomm SoCs
Domain
Semiconductor / Hardware Engineering / System-on-Chip
Required skills
RTL design, Micro-architecture, Specification, Testbench development, Functional verification, Power-aware verification, Performance verification, Debug infrastructure, Silicon validation, SoC integration
Responsibilities
Define and design next-gen Qualcomm coherent and non-coherent interconnect fabric & related IPs; Develop robust, scalable testbench & drive functional, power aware, performance, security, debug feature verification of Next-gen Qualcomm coherent and non-coherent interconnect fabric & related IPs; Partner with SoC Architecture, verification, physical design team, Soc Floorplan and core teams globally; Ensure Interconnect meeting all performance requirement, and with silicon validation team to co-relate pre-silicon and post silicon design assumptions; Responsible for micro-architecting all relevant debug hooks in NoC Infrastructure to help root cause silicon issues.
Seniority
Sr. Lead/Staff, hands-on IC
