ASIC Physical Design
1,421 open positions
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<Data Center> Program Manager MediaTekHsinChu 4mo Ensures on-time delivery of ASIC designs by coordinating multi-disciplinary efforts across design, verification, physical design, test vehicles, DFT, packaging, operations, and supply chain.
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Lead Design Engineer CadenceBANGALORE 4mo Designing digital logic and data path systems using Verilog and RTL, ensuring timing and interface compliance.
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Physical Design Signoff CAD Engineer NVIDIAIsrael, Yokneam 4mo Developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs.
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Senior Engineer, GPU RTL Power Samsung Electronics3900 N Capital of Texas Hwy, Austin, TX, USA $124k–$124k4mo Senior GPU RTL Power Engineer optimizing energy efficiency for Samsung's next-generation mobile GPUs used in premium smartphones.
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SOC Integration Engineer
MatXMountain View
$160k–$160k4mo
Design and integrate high-performance System-on-Chip (SoC) RTL for AGI compute platforms, managing subsystem integration, timing constraints, and automation flows.
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Staff Digital Design Engineer AnalogdevicesIndia, Bangalore, RMZ 4mo Lead complex digital design projects and provide technical leadership for system-level architecture.
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Hardware Engineering Architect, Networking Devices JabilRemote 4mo Lead system-level architecture planning for next-generation Ethernet switch platforms, translating customer use cases into scalable architectures for RFQ/RFI and new business engagements.
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Memory Systems Performance & Workload Architect - DMTS/SMTS Micron2 Locations 4mo Lead workload-driven memory architecture and performance strategy across mobile and server-class platforms, translating real-world application behavior into next-generation memory architecture and product features.
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Chip Architect NxpPune 4mo Defines and delivers cutting-edge systems-on-chip (SoC) architectures for next-generation products, translating product requirements into robust architecture while balancing performance, power, area, and cost.
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Physical Design Engineer Texas InstrumentsBengaluru, Karnataka, India 4mo Physical design of complex mixed-signal SoC/ASIC blocks for audio applications, taking RTL through synthesis to tape-out.
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FPGA Lead Designer ON SemiconductorBangalore, Karnataka, India 4mo Design, implement, and support bring-up of FPGA solutions for image sensor test, development, and reference systems hardware.
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CDI - Ingénieur design digital (RTL) avec compétences en développement firmware H/F StmicroelectronicsGrenoble, France 4mo Define digital design methodologies, IP structures, and assembly processes for mixed-signal SoCs in the Imaging division.
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Sr. Principal Engineer, Design Technologist GlobalFoundriesUSA - Texas - Richardson $171k–$171k4mo Enable efficient silicon development by aligning design methodologies with foundry technologies to improve PPA (Power, Performance, Area) and ensure manufacturability for SoC designs.
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Forward Error Correction Engineer MarvellCordoba, Argentina 4mo Design and validate forward error correction (FEC) and DSP schemes for optical coherent transceivers to enable error-free communications in hardware.
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Hardware Engineer Frontgrade Gaisler ABRemote 4mo Designing processor and peripheral IP cores for system-on-chip solutions used in space and safety-critical systems.
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Principal Engineer, DDR & NOC Architecture↗ RivianRemote, US 4mo Lead the definition and evolution of next-generation Network-on-Chip (NOC) and DDR memory controller architecture for complex SoCs, owning the on-chip data fabric and external memory subsystem.
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ASIC Engineering Digital Design Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 12-16 Years | Pune) CiscoPune, India 4mo Lead digital design and architecture for high-speed optical interconnects (100G, 200G, 400G) and silicon photonics modules, managing the full ASIC lifecycle from RTL to tapeout.
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Senior FPGA Design Engineer AxiadoSan Jose, CA, us 4mo Designing, verifying, and debugging FPGA systems for platform security management and ransomware detection in cloud datacenters and 5G infrastructure.
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Hardware Engineer (Compute Server) UbiquitiTaipei 4mo Design next-generation high-density storage server solutions (NAS, SAN, unified storage) focusing on system architecture, signal integrity, and thermal management.
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Senior Staff Engineer, Physical Design - NoC SifiveBengaluru, Karnataka, India 4mo Own and drive the implementation of massive, high-bandwidth interconnects (NoC) and Uncore subsystems from RTL to GDSII, acting as a bridge between architecture and physical design to optimize PPA.
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Senior Staff/ Staff Design Engineer SilabsSingapore 4mo Designing digital blocks and SoC infrastructure for low-power MCU and Wireless products.
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SOC Micro-Architect and RTL Designer
MatXMountain View (HQ) or Remote
$160k–$160k4mo
Designing high-performance silicon micro-architecture and RTL for compute, memory management, and high-speed connectivity subsystems for AGI training workloads.
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PD Intern EtchedSan Jose 4mo Realizing front-end designs in silicon to improve iteration speed to final signoff for inference-focused AI hardware.
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PCIe design Architect BroadcomIND-Bangalore Electronic City - S1 4mo Designing and architecting PCIe subsystems and SoCs for Broadcom products.
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