ASIC Physical Design
1,421 open positions
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Lead Physical Design Engineer NxpHyderabad, IN 4mo Lead physical design and implementation of complex, high-performance semiconductor integrated circuits (AI NPUs) from RTL synthesis through timing convergence.
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Senior Hardware Design Engineer, High Speed Networking Arista-NetworksNashua, NH, us 4mo Designing high-speed networking and Ethernet products for enterprise campuses, hyperscale datacenters, and AI clusters.
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Firmware Engineer AkkodisEastern England, UK 4mo Design, develop, integrate, and verify FPGA and SoC-based systems for defence and mission-critical applications using OpenCPI frameworks.
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Senior RTL Integration Engineer NVIDIAIsrael, Yokneam 4mo Lead system-level integration of complex RTL builds into high-performance Network Adapter Silicon chips.
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HBM SoC RTL Design Engineer MicronFolsom, CA $146k–$146k4mo Design, develop, and integrate next-generation HBM SoC logic die, collaborating with architecture, verification, and physical design teams to meet power, performance, area, and schedule targets.
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AI Computing Platform Hardware Planner MediaTekHsinChu 4mo Drive competitive benchmarking of AI computing platforms (CPUs, GPUs, NPUs) by analyzing performance metrics like perf/W and tokens/sec to compare MediaTek's solutions against competitors.
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Senior Staff ASIC Design Engineer AxiadoHyderabad, TS, in 4mo Design and implement System-on-Chip (SoC) micro-architecture, RTL coding, synthesis, and timing closure for secure AI infrastructure.
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AMBA Architect ArmCambridge, United Kingdom 4mo Designing next-generation Arm system architectures focusing on memory systems, address translation, and virtualization-aware interfaces.
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Staff Digital IC Design Engineer AnalogdevicesSingapore, Kallang 4mo Designing and implementing digital ICs and micro-architectures for Optical Control ICs serving AI datacenters.
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Senior/Staff Digital Design Engineer OlixAustin, TX 4mo Architect, design, and implement high-throughput digital pipelines for real-time data-processing silicon in advanced CMOS nodes.
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Senior ASIC Design Engineer – Processor Subsystem EspaceSaratoga, CA 4mo Design, configuration, integration, and verification planning of Arm processor IP and associated subsystem components for satellite IoT connectivity ASICs.
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Principal System Engineer (f/m/d) Renesas-ElectronicsRemote 4mo Define and drive the system architecture of next-generation sensor IC solutions for automotive and industrial markets, translating system requirements into silicon architectures.
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Principal Hardware Engineer HpeSunnyvale, California, United States of America $154k–$311k4mo Design, analyze, develop, and evaluate electrical/electronic parts, components, sub-systems, and integrated circuitry for high-end routing platforms from concept to mass production.
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Lead Digital Design Engineer Texas InstrumentsBengaluru, Karnataka, India 4mo Lead a SoC Front End team to own SoC integration of complex ARM architecture based SoCs up to RTM, ensuring testability, reliability, and manufacturability for AI-driven data centers and humanoid systems.
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Staff FPGA Engineer (Future Forward) IntuitiveSunnyvale, CA, us 4mo Design, implement, and test complex FPGA designs for electronic boards in robotic surgical systems, integrating them into complete solutions for human use.
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Senior Hardware Engineer Siemens-EdaNew Cairo, EGY, Egypt $34k–$34k4mo Design and develop FPGA IPs, integrate third-party IP, and create simulation/test environments for complex electronic systems.
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ASIC Technical Program Manager EtchedSan Jose 4mo Own program coordination across Physical Design, DFT, DV, and RTL teams for ASIC development cycles, managing external vendors and driving technical execution for tape-outs.
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Staff Engineer, GPU RTL Power Management Samsung Electronics3900 N Capital of Texas Hwy, Austin, TX, USA $151k–$151k4mo Design and develop power management/SoC interface RTL blocks and subsystems for next-generation mobile GPU IPs to enable high-performance computing devices.
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ASIC Physical Design Engineer CiscoArmenia 4mo Lead macro-level RTL-to-GDSII physical implementation and signoff for complex SoC and block-level projects, translating architecture into optimal physical design.
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?Softwareentwickler FPGA (d/w/m) Konstanz, BADEN_WUERTTEMBERG 5mo Design, implementation, and documentation of FPGAs for image processing and communication applications.
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ASIC Implementation Engineer BroadcomUSA-CA San Jose Innovation Drive $120k–$120k5mo Physical Design Engineer responsible for taking Netlist to silicon tape-out for next-generation AI designs.
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