<Data center>Senior Low Power Design Methodology Engineer
Core
Drive and deploy advanced SoC-level power optimization techniques for next-generation data center products.
Role type
Senior IC low-power design methodology engineer
Builds
Next-generation data center products
Domain
Semiconductor design / Data center infrastructure
Deliverable
production ML models | product features
Required skills
SoC-level power optimization, RTL design collaboration, synthesis integration, physical design collaboration, power estimation, power analysis across design stages, silicon power correlation, power-related debug
Preferred skills
Tier-1 customer partnership, actionable power reduction recommendations
Technologies
RTL, synthesis, physical design tools
Responsibilities
Drive and deploy advanced SoC-level power optimization techniques; Perform power estimation and analysis across design stages; Partner with tier-1 customers to define power specifications; Support silicon power correlation and power-related debug during sample back
