Principal STA Engineer
Core
Drive timing convergence for high-performance System-on-Chips (SoCs) through setup, analysis, and sign-off across multi-mode, multi-corner, and multi-voltage domains.
Role type
Principal STA Engineer (ASIC Physical Design)
Builds
High-speed interface SoCs (DDR, PCIe, HBM, D2D) and digital logic blocks
Domain
Semiconductor / VLSI / ASIC Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static Timing Analysis (STA), Timing Closure, Multi-Corner Multi-Voltage (MCMV) analysis, Clock Tree Synthesis (CTS), ECO implementation, Automation scripting, Deep sub-micron technology knowledge (28nm and below), High-speed interface protocols
Preferred skills
Experience with Synopsys PrimeTime or similar tools, RTL to GDSII flow knowledge, Library/Memory collateral understanding, Variation/Aging aware design
Technologies
Synopsys/Cadence tools, PrimeTime, DDR, PCIe, HBM, D2D
Responsibilities
Perform timing analysis and closure at Partition/Sub-system/FC levels, Develop and execute timing ECO strategies, Create automation scripts for STA methodology, Evaluate timing tools across different technology nodes, Debug implementation issues and propose creative solutions, Influence APR and design teams for convergence
Seniority
Principal, hands-on IC with strategic sign-off leadership
