RTL Design Engineer
Core
Designing low-power RTL and microarchitecture for System LSI, Mobile SoCs, and AI/ML solutions.
Role type
Senior RTL Design Engineer
Builds
ASICs and SoCs for Samsung Electronics products
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features
Required skills
Low power RTL design, microarchitecture, synthesis, timing closure, power estimation, Verilog/System Verilog, SoC integration, arithmetic unit design, floating point data path design, ASIC design tools (VCS, Verdi, Design Compiler), scripting (Shell, Perl, Python), C language, AXI/APB bus protocols, hardware architecture exploration, performance modeling
Preferred skills
PCIe/UCIe protocols, AI/Near Memory acceleration domain experience
Technologies
VCS, Verdi, Design Compiler, Spyglass, PTPX
Responsibilities
Optimize microarchitecture and RTL for area and power reduction, sign off RTL and synthesized netlist for physical design and tape-out, conduct PPA (Power, Performance, Area) analysis
Seniority
Senior, hands-on IC
