Senior Physical Design Methodology Engineer, PPA Fusion Compiler
Core
Developing efficient physical design methodologies and ML-based solutions for high-speed communication devices and graphics processors to optimize Power, Performance, and Area (PPA).
Role type
Senior Physical Design Methodology Engineer (PPA Fusion Compiler)
Builds
High-speed communication devices, graphics processors, and System-on-Chips (SOCs)
Domain
Semiconductor / Hardware Design / AI for Physical Design
Deliverable
production ML models | product features
Required skills
Physical Design Engineering, Machine Learning solution development, Floor planning, Clock and Power distribution, Place and Route (P&R), Timing analysis and closure, IR/Signal-EM convergence, Power and noise analysis, Hierarchical design approach, Design for Yield and Manufacturability, Scripting for PPA improvement
Preferred skills
Chip assembly, Back-end verification, Thermal management, Standard industry PnR tools knowledge
Technologies
P&R tools, Timing analysis tools, Power analysis tools, EM/IR analysis tools, Scripting languages
Responsibilities
Develop unique solutions to state-of-the-art physical design problems, Participate in developing flow and tool methodologies for P&R and verification, Perform data-based analysis and algorithmic solutions for PPA check and improvement
Seniority
Senior, hands-on IC
