SOC Micro-Architect and RTL Designer
Core
Designing high-performance silicon micro-architecture and RTL for compute, memory management, and high-speed connectivity subsystems for AGI training workloads.
Role type
Senior IC silicon micro-architect and RTL designer
Builds
ASICs and SOCs for high-performance compute, memory management, and high-speed connectivity
Domain
Semiconductor hardware design for AGI/GenAI
Deliverable
production ML models | product features
Required skills
Silicon micro-architecture design, RTL design (SystemVerilog), ASIC/SOC design flow, high-performance compute concepts (CPUs, GPUs, accelerators), design synthesis, equivalence checking, DFT, physical design concepts, Python/C/C++ scripting
Preferred skills
PCIe/HBM/DMA/Die-to-die subsystem implementation, verification/emulation platforms, silicon debug and bring-up
Technologies
SystemVerilog, Python, C, C++, ASIC, SOC, DFT, Physical Design
Responsibilities
Contribute to architecture-to-design methodology across blocks and full-chip; Own subsystem or chip-level design deliverables from micro-architecture to sign-off; Plan and drive micro-architecture reviews and timing/area closure; Collaborate with verification and physical design teams for performance-power-area optimization
Seniority
Senior, hands-on IC
