Staff Engineer, Digital Design Engineering
Core
Own specification, micro-architecture, and RTL design of digital modules while influencing chip architecture.
Role type
Staff Digital Design Engineer (RTL/Architecture)
Builds
Digital IPs and functional blocks for semiconductor chips
Domain
Semiconductor / Digital Logic Design
Deliverable
production ML models | product features
Required skills
RTL coding, digital logic design, timing closure, lint checks, clock domain crossing (CDC) analysis, static timing analysis, synthesis, formal equivalence, ECO flows, scripting, post-silicon debug
Preferred skills
Audio and/or DSP fundamentals, mentoring junior engineers
Technologies
RTL, Lint, Synthesis tools, Static-timing-analysis tools
Responsibilities
Develop module specifications and micro-architecture; Provide technical and managerial leadership to design engineers; Guide junior engineers on timing constraints and synthesis; Collaborate with verification and physical design teams for coverage and timing closure; Support post-silicon debug activities
Seniority
Staff, hands-on IC with technical leadership
