ASIC Engineering Digital Design Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 12-16 Years | Pune)
Core
Lead digital design and architecture for high-speed optical interconnects (100G, 200G, 400G) and silicon photonics modules, managing the full ASIC lifecycle from RTL to tapeout.
Role type
Senior IC ASIC Digital Design Leader
Builds
High-performance optical transceivers, Co-packaged Optics (CPO), and silicon photonic platforms for data center networking.
Domain
Semiconductor / Silicon Photonics / High-Speed Optical Interconnects
Deliverable
production ML models | product features | infrastructure
Required skills
RTL design (SystemVerilog), CPU subsystem design, FSM design, complex SoC architecture, SerDes/DSP IP integration, DFT, synthesis, timing closure, FPGA prototyping, verification coverage analysis, backend design automation scripts.
Preferred skills
Master's degree in EE/Electronics, 6+ years technical leadership experience, deep knowledge of feedback/control systems and stability.
Technologies
SystemVerilog, SerDes, D2D PHY IP, AXI, SPI, I2C, CDC/RDC, LEC, ATE, FPGA.
Responsibilities
Lead design activities from Pre-Silicon RTL to GDS2 signoff and Post-Silicon validation; define digital architecture and interface requirements; lead block-level development of high-speed IPs; support firmware architecture and verification; review verification coverage and sign off on metrics; support backend activities including synthesis, timing closure, and low power design.
Seniority
Senior, hands-on IC with technical leadership