ASIC Engineering Digital Design Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 12-16 Years | Pune)
Core
Lead digital design for silicon photonics and high-speed optical interconnects (100G-400G), managing the full ASIC lifecycle from RTL architecture to tapeout and post-silicon validation.
Role type
Senior IC ASIC Digital Design Lead
Builds
High-performance optical transceivers, Co-packaged Optics (CPO), and silicon photonic platforms for data center networking.
Domain
Semiconductor / Silicon Photonics / High-Speed Optical Interconnects
Required skills
RTL design (SystemVerilog), CPU subsystem design, FSM design, complex SoC architecture, SerDes (PAM4), DFT, synthesis, timing closure, FPGA validation, cross-functional technical leadership
Preferred skills
Master's degree in EE, 12-16 years experience, 6+ years technical leadership, knowledge of feedback/control systems, FW architecture understanding
Technologies
SystemVerilog, SerDes, FPGA, AXI, SPI, I2C, APB, CDC, LEC, DFT tools
Responsibilities
Define digital architecture and interface requirements; lead block-level development of high-speed IPs (ODSP, SerDes, control functions); support full-chip integration and verification; drive post-silicon bring-up and release; review verification coverage and sign off on metrics; support backend activities (synthesis, timing, low power).
Seniority
Senior, hands-on IC with leadership
