ASIC Physical Design
1,421 open positions
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Digital IC designer - Image processor MediaTekHsinChu 3mo Design industry-leading image signal processors (ISP) for diverse products including smartphones, tablets, automotive, and home entertainment.
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Physical Design Engineer CerebrasHeadquarters/Sunnyvale Office $230k–$230k3mo Design and analysis of 3D integrated products, combining traditional ASIC/SoC physical design with packaging, power, clock, and cooling analysis.
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Staff SoC Performance Architect – Next-Generation Server Platforms ArmMultiple locations $198k–$198k3mo Architecting performance for next-generation server platforms by analyzing real-world workloads, silicon behavior, and system-level design to optimize scalability and efficiency.
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration SilabsAustin $143k–$143k3mo Develop complex, highly integrated, low-power System on a Chip (SoC) architectures and digital subsystems for wireless IoT applications.
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LPDDR Product Architect MicronSan Jose, CA $208k–$208k3mo Architecting LPDDR-based memory module solutions for AI inference at the edge, translating system-level insights into real-world hardware products.
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Senior/Staff Design Engineer GlobalFoundriesSanta Clara, US $69k–$69k3mo Developing and owning RTL development of AI-enabled RISC-V CPU cores, focusing on micro-architecture, performance, power, and area optimization.
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Experienced Digital Design Engineer Texas InstrumentsRa'anana, Israel 3mo Define, develop, and debug silicon micro-architecture design for wireless MCU products targeted at Industrial markets.
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Sr. EMIR Engineer, Annapurna Labs - Cloud Scale Machine Learning
AmazonCupertino, California, United States
$159k–$159k3mo
Design and analyze power grids for SoCs, developing test cases to model demand currents and sign off EMIR analysis taking into account board and package impact.
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Senior Hardware Design Engineer Arista-NetworksBengaluru, KA, in 3mo Designing high-speed networking and Ethernet products for enterprise campuses, hyperscale datacenters, and AI clusters.
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Staff/ Sr Staff/ Principal Engineer, Digital Design Renesas-ElectronicsRemote 3mo Lead RTL design and development of complex IPs and subsystems within MCU SoCs, ensuring compliance with performance, power, and area (PPA) targets.
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Senior Principal Physical Design Engineer NxpLeuven 3mo Lead and execute advanced physical design activities for complex SoC and IP blocks, achieving performance, power, and area targets for cutting-edge semiconductor products.
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Senior Digital Design Engineer - High-Speed I/O and Photonics NVIDIAUS, CA, Santa Clara $136k–$136k3mo Designing high-speed digital front-end and back-end for silicon photonics IPs and chips, enabling AI systems and high-performance networking.
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Principal Physical Design Engineer HpeSunnyvale, California, United States of America $174k–$353k3mo Developing scalable RTL-to-GDS physical design flows and methodologies for advanced ASIC designs to ensure high-performance silicon delivery.
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Senior Engineer, GPU RTL Design Samsung Electronics3900 N Capital of Texas Hwy, Austin, TX, USA $124k–$124k3mo Design and develop complex RTL blocks and subsystems for Samsung's next-generation mobile GPU IPs, translating architectural specifications into efficient, scalable hardware designs for high-performance computing devices.
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Senior Director - System Architecture AmbiqmicroincAustin HQ 3mo Lead architect developing next-generation ultra-low-power, AI-based System on Chip (SoC) architectures for wearable, IoT, and mobile products.
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Physical Design Manager CiscoCaesarea, Israel 3mo Lead the backend methodology and flow development from RTL to GDS for high-quality VLSI designs, providing strategic and technical leadership to a team of engineers.
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Emulation Engineer - Hardware Prototyping (HAPS) EtchedSan Jose $150k–$150k3mo Own HAPS bring-up by taking RTL from design teams and getting it running on prototypes through partitioning, multi-FPGA timing closure, clocking, memory mapping, and full-chip assembly.
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单板硬件工程师 HuaweiAscend Internet & Server Hardware Development Dept 4mo Design and deliver hardware architecture and system solutions for Huawei computing clusters (AI clusters, servers, boards, modules), focusing on innovation, DFX, and performance.
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Staff Electrical Engineer – FPGA / MPSoC Systems & Digital Signal Processing SirenOptHeadquarters $160k–$160k4mo Lead architecture, design, implementation, and validation of high-performance FPGA/MPSoC systems and digital signal processing pipelines for a metrology platform that analyzes micro- and nano-materials.
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CPU Physical Design Engineer IntelUS, Texas, Austin $142k–$269k4mo Physical design implementation of custom CPU designs from RTL to GDS for manufacturing, focusing on power efficiency and timing closure.
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Lead Design Engineer CadenceBANGALORE 4mo Designing digital logic and data path systems using Verilog and RTL, ensuring timing and interface compliance.
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