PD Layout expert
Core
Developing physical design solutions for high-growth markets including AI-driven data centers and humanoid systems.
Role type
Senior IC Physical Design Engineer (SoC Layout)
Builds
SoC layouts, power grids, and IR drop validation for advanced computing and automation systems.
Domain
Semiconductor / VLSI Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Floorplan creation, Congestion analysis, DRC/LVS verification, Power-grid design, IR drop validation, ECO implementation, Scripting (TCL/Perl/Python), EDA tool expertise
Preferred skills
Layout closure in Innovus, Correct-by-construction methodologies, AI/ML integration in design flows
Technologies
Innovus, EDA tools, TCL, Perl, Python
Responsibilities
Drive layout closure and establish correlation with signoff; Drive SoC layout (FP), Power-grid design, and IR drop validation; Collaborate with timing, ATD, ESD, and physical verification teams; Drive ECO implementation for DRC and LVS fixes; Implement correct-by-construction approaches using advanced EDA tools.
Seniority
Senior, hands-on IC