SOC Integration Engineer
Core
Design and integrate high-performance System-on-Chip (SoC) RTL for AGI compute platforms, managing subsystem integration, timing constraints, and automation flows.
Role type
Senior IC silicon micro-architect / SoC integration engineer
Builds
Full-chip SoC RTL designs for high-performance GenAI workloads
Domain
Semiconductor hardware design / AI compute infrastructure
Deliverable
production ML models | product features
Required skills
SystemVerilog, Python/Perl scripting, SoC RTL integration, high-speed interconnect standards (UCIE), memory management, clock/reset methodology, timing constraint validation, DFT wrapper integration, design synthesis, emulation platforms
Preferred skills
AI-driven automation tools, logical equivalency verification, physical design collaboration
Technologies
SystemVerilog, Python, Perl, UCIE, DFT, emulation platforms
Responsibilities
Drive evolution of silicon architecture-to-design methodology for seamless subsystem integration; Partner with subsystem owners to develop SoC top-level RTL; Implement automation for on-the-fly generation of SoC top-level RTL; Collaborate with physical design teams on floorplan connectivity; Establish clock and reset methodologies; Define SoC-level timing constraints; Provide technical support to package and board teams for pin requirements and netlists
Seniority
Senior, hands-on IC
