Member of Technical Staff, AI‑Optimized Memory Digital Design Engineer / Microarchitect
Core
Design and implement high-performance, tightly coupled memory microarchitectures for AI workloads, translating architectural intent into silicon-proven implementations.
Role type
Senior IC digital design engineer (AI memory microarchitecture)
Builds
Next-generation, high-performance memory solutions for AI systems
Domain
Semiconductor / AI hardware / Memory systems
Deliverable
production ML models | product features | infrastructure
Required skills
Digital design, microarchitecture development, SystemVerilog, synthesis, PPA estimation and optimization, SoC-level behavior reasoning, high-level programming (C/C++, Python)
Preferred skills
Memory interfaces and systems concepts, RTL cost and feasibility analysis
Technologies
SystemVerilog, C, C++, Python
Responsibilities
Translate architecture requirements into efficient, scalable microarchitectures; Design and review SystemVerilog designs for memory systems; Perform synthesis and early analysis to optimize area, power, and timing; Compose microarchitecture documentation; Drive technical decisions by evaluating tradeoffs across microarchitecture and implementation constraints
Seniority
Senior, hands-on IC
