Physical Design Signoff CAD Engineer
Core
Developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs.
Role type
Physical Design Signoff CAD Engineer
Builds
Networking chips and SOCs
Domain
Semiconductor / Networking Silicon
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical Design, Backend CAD, Static Timing Analysis (STA), Timing closure methodologies, Power Estimation, Power Integrity, Formal Equivalence, Tcl, Perl, Python
Preferred skills
Signoff domain expertise (PrimeTime, PrimePower, RedHawk, Formality), Versatility
Technologies
PrimeTime, PrimePower, RedHawk, Formality
Responsibilities
Develop physical design and STA flows; Collaborate with block owners and full Chip STA engineers for convergence; Create solutions for state-of-the-art physical design problems; Develop flow and tool methodologies for timing, power, noise, IR-drop, EM, and back-end verification.
Seniority
Mid-level, hands-on IC
