PD Intern
Core
Realizing front-end designs in silicon to improve iteration speed to final signoff for inference-focused AI hardware.
Role type
Physical Design Intern (ASIC/SoC)
Builds
Custom silicon chips and racks for frontier intelligence inference workloads.
Domain
Semiconductor hardware engineering / AI Infrastructure
Deliverable
production ML models
Required skills
High-speed digital logic, ASIC/SoC design concepts, SystemVerilog, UVM, Python, physical design flows, test bench writing
Preferred skills
Modern ML/LLM model architectures, numerical representations in RTL, clocking and reset schemes, formal verification
Technologies
SystemVerilog, UVM, Python, physical design tooling
Responsibilities
Synthesize design blocks, automate final design checks, advise RTL design decisions, run physical design flows
Seniority
Intern
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