Lead Design Engineer
Core
Designing digital logic and data path systems using Verilog and RTL, ensuring timing and interface compliance.
Role type
Lead Design Engineer (RTL/Verilog)
Builds
Digital logic circuits, data path designs, and interface protocols for semiconductor products.
Domain
Semiconductor hardware design / Digital IC design
Deliverable
production ML models | product features | infrastructure
Required skills
Verilog coding, RTL design, data path design, RTL linting (LINT), Static Timing Analysis (SDC), Clock Domain Crossing (CDC), synthesis flow, timing constraints, testbench creation, simulation, interface protocols (UCIe, PCIe, USB, MIPI, HDMI)
Responsibilities
Write Verilog code for data path designs, perform RTL checks and timing analysis, create testbenches and run simulations, ensure compliance with interface protocols.
Seniority
Lead, hands-on IC
