High‑Speed RTL Design Engineer
Core
Design and implement timing-critical RTL blocks for high-speed memory and storage solutions, ensuring robust logic for synthesis and timing closure.
Role type
Senior IC high-speed RTL design engineer
Builds
Control FSMs, register banks, telemetry datapaths, and clock/reset logic for DRAM, NAND, and NOR memory chips
Domain
Semiconductor / High-speed digital design / Memory and storage
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, Verilog, FSM design, reset synchronization, clock-domain crossing (CDC), setup/hold timing fundamentals, critical-path sensitivity, multi-mode behavior, mixed-signal interaction awareness, RTL lint, CDC checks, synthesis, static timing analysis (STA), DFT-friendly practices, UPF, LEC
Preferred skills
PMICs, mixed-signal SoCs, industry-standard specifications, Python/Tcl scripting, RTL-DV-PD handshakes
Technologies
SystemVerilog, Verilog, UPF, LEC
Responsibilities
Design and implement timing-critical RTL blocks including control FSMs, register banks, and telemetry datapaths; Write RTL robust to tight setup/hold margins, clock skew, and PVT variation; Implement and review clock-domain crossings (CDC) and reset logic; Integrate RTL blocks into subsystems and resolve port-list mismatches and mode interactions; Debug RTL and integration issues using simulation waveforms; Clarify design intent and fix RTL issues uncovered during verification; Participate in design reviews and maintain clear documentation
Seniority
Senior, hands-on IC
