IP RTL Design Engineer
Core
Develop high-performance PHY IP for HBM and LPDDR memory interfaces, focusing on RTL design, verification, and post-silicon support.
Role type
Senior IC RTL Design Engineer (Memory PHY)
Builds
HBM and LPDDR PHY IP blocks for customer SoCs
Domain
Semiconductor / Memory / High-speed interfaces
Deliverable
production ML models | product features | infrastructure
Required skills
Verilog/SystemVerilog, SDC constraints, Synthesis, Static Timing Analysis (STA), LINT, CDC, DFT, ATPG, Memory-PHY design, High-speed interface IP
Preferred skills
LPDDR project experience, HBM project experience
Technologies
Verilog, SystemVerilog, IPXACT, PreSTA
Responsibilities
Write, verify, and maintain synthesizable RTL for LPDDR PHY blocks; Write SDC constraints, synthesize and ensure timing closure; Setup and run IPXACT, LINT, CDC, SDC, PreSTA, DFT and ATPG checks; Support silicon validation bring-up and debug post-silicon issues
Seniority
Senior, hands-on IC
