Senior Staff Engineer, Physical Design - NoC
Core
Own and drive the implementation of massive, high-bandwidth interconnects (NoC) and Uncore subsystems from RTL to GDSII, acting as a bridge between architecture and physical design to optimize PPA.
Role type
Senior Staff Physical Design Engineer (NoC/Uncore)
Builds
High-performance RISC-V compute platforms and IP for AI, automotive, data center, and mobile applications.
Domain
Semiconductor chip design, specifically RISC-V architecture and physical implementation.
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical design implementation (synthesis, place & route, signoff), NoC/Uncore architecture expertise, hierarchical floorplanning, PPA optimization, RTL reading, cross-abstraction co-design, tool proficiency (Synopsys/Cadence), mentorship
Preferred skills
System-level data flow understanding, micro-architecture influence, long-distance timing closure, repeater/pipeline-stage insertion, global timing closure
Technologies
Synopsys, Cadence, RTL, GDSII, NoC, Uncore
Responsibilities
Lead NoC implementation including synthesis, place & route, and signoff; Drive cross-abstraction-layer co-design with architecture and RTL teams; Solve NoC-specific physical bottlenecks like timing closure and clock distribution; Architect top-level floorplanning and macro placement; Optimize implementation for aggressive PPA goals; Drive methodology and automation for physical design flows; Mentor junior engineers
Seniority
Senior Staff, hands-on IC with mentorship responsibilities