Senior ASIC Floorplan Design Engineer
Core
Design and optimize floorplans for next-generation GPUs and SoCs, influencing early design decisions to solve timing, routing congestion, and area issues.
Role type
Senior IC ASIC Floorplan Design Engineer
Builds
High-performance GPUs and System-on-Chip (SoC) architectures
Domain
Semiconductor / VLSI / Hardware Engineering
Deliverable
production ML models | product features
Required skills
VLSI design, Computer Architecture, Verilog, System Verilog, Physical Design methodologies, Chip floorplanning, Power/Clock distribution, Packaging, Place & Route (P&R), Timing closure, Python, Perl, C/C++
Preferred skills
Large-scale ASIC floorplan development
Technologies
Verilog, System Verilog, Python, Perl, C/C++
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