Principal Engineer, Physical Design
Core
Lead end-to-end RTL-to-GDSII execution for complex, high-performance SoCs, ensuring predictable tapeouts and first-pass silicon success.
Role type
Principal Engineer, Physical Design
Builds
Complex, high-performance System-on-Chip (SoC) designs
Domain
Semiconductor / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Incorrect mapping in thought, correcting to: physical silicon chips)
Required skills
Full-chip physical design, floorplanning, power planning, placement & routing, clock architecture/CTS, extraction, signoff methodologies (STA, SI, IR/EM), DRC/LVS closure, automation scripting (TCL, Python, Perl), low-power design (UPF/CPF)
Preferred skills
None stated
Technologies
TCL, Python, Perl, STA, SI, IR/EM, UPF/CPF
Responsibilities
Lead end-to-end RTL-to-GDSII execution including synthesis, floorplanning, placement, CTS, routing, and signoff; Own timing, power, and physical signoff strategy; Establish and enforce DRC/LVS closure methodologies; Partner with RTL, DFT, packaging, and system teams; Define and deploy automated design methodologies; Champion low-power design strategies
Seniority
Principal, hands-on IC