ASIC Physical Design
1,420 open positions
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Senior/Principal Physical Design Engineer FractileThe Crescent 3mo End-to-end implementation of complex IC physical designs from synthesis to sign-off to increase clock speed for AI inference systems.
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Team Leader - Digital IC design AumovioBengaluru, KA, in 3mo Leading a digital IC design team in Bangalore, coordinating resources and processes for automotive product development.
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Lead Design Engineer CadencePUNE 04 3mo Lead physical design implementation for state-of-the-art interface IPs (DDR, PCIe, etc.) and test chips at advanced process nodes (7nm/5nm/3nm/2nm), optimizing for performance, power, and area.
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ASIC Engineer Staff HpeBengaluru, Karnātaka, India 3mo Lead VLSI design, verification, and implementation for complex HPE products and platforms, driving innovation and integrating new technologies.
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VLSI RTL DV Technical Project Manager/Program manager HCLTechIndia 3mo Drive end-to-end program delivery for VLSI and silicon development projects, ensuring alignment with customer processes, quality expectations, and regulatory requirements.
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Senior Digital Design Engineer for Korea ISG ON SemiconductorSeoul, Korea, Republic of 3mo Designing CMOS image sensors from RTL to chip for consumer and automotive sensor solutions.
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Debug/Trace/Profiling Design Engineer SifiveLa Ciotat, France 3mo Designing industry-leading debug, trace, and profiling IP for RISC-V processor cores to enable high-performance SOC designs across AI, automotive, and data center markets.
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Staff/Principal Hardware System Design Engineer MicronSan Jose, CA $202k–$202k3mo Architecting SSD tester equipment platforms and defining system-level hardware architecture for next-generation memory test solutions.
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SRAM Design Engineer MediaTekBangalore 3mo Designing Fast Cache instances (FCI) for xPU (CPU/GPU) systems and optimizing SRAM for power, timing, area, and yield.
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System IC Architect - Advanced Power Systems NxpRemote 3mo Define next-generation Point of Load (PoL) power solutions and System-in-Package (SiP) architectures for high-performance core power in automotive and AI compute platforms.
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Staff Application Engineer (experience in FPGA design/ Verilog) Renesas-ElectronicsZhubei, tw 3mo Lead application/system design, training, and technical support for customers regarding Renesas Configurable Products, specifically FPGA and GreenPAK.
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Manager, Physical Design Circuit and Signoff CAD NVIDIAIsrael, Yokneam 3mo Lead a team responsible for tracking and executing end-to-end activities spanning internal CAD flow development and circuit-level studies to support silicon sign-off for NVIDIA's advanced chips.
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Principal NoC IP Micro-Architect AlteraPenang 15, Penang, Malaysia 3mo Designing logic, RTL coding, and simulation for Network on Chip (NoC) IPs and FPGA subsystems for full chip integration.
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Digital Senior Design Engineer CienaOttawa $109k–$109k3mo Design power and area optimized functional blocks for Ciena's Wavelogic optical fiber transmission products.
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SoC Design Engineer ArmBudapest, Hungary 3mo Designing and integrating RTL subsystems and microarchitecture for complex System-on-Chip (SoC) processing systems.
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Staff/Senior Staff Physical Design Engineer (Technical Lead) Enchargeai36Remote 3mo Lead physical design for next-generation in-memory computing silicon products, optimizing PPA for edge-to-cloud applications.
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Micro-Architect and RTL Designer
MatXMountain View (HQ) or Remote
$160k–$160k3mo
Designing high-performance silicon micro-architecture and RTL for compute, memory management, and high-speed connectivity blocks to support AGI workloads.
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Staff Engineer, Digital Design Engineering AnalogdevicesIndia, Bangalore, RMZ 3mo Lead the development, curation, and delivery of reusable strategic digital IPs (accelerators, datapath, high-speed interfaces) to accelerate product development across business units.
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Staff Digital Design Engineer (f/m/div)↗ Infineon TechnologiesValencia, VC, ES 3mo Staff Digital Design Engineer responsible for digital block architecture, RTL design, verification, and synthesis for automotive-grade integrated circuits.
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EDA Tools Hardware Engineer IntelUS, California, Santa Clara $142k–$142k3mo Develop and maintain full-chip physical implementation flows, including floor planning, hierarchical block integration, placement, routing, power grid planning, and clock tree synthesis to enable scalable SoC assembly.
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Micro-architect/Logic Designer, Coherent Interconnect Samsung Electronics3655 N 1st St, San Jose, CA, USA $151k–$151k3mo Leading micro-architecture development of custom coherent interconnect IP and last level cache blocks for high-performance computing devices.
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Senior FPGA Engineer (DV Equities) DvtradingLondon 3mo Architect and deliver ultra-low-latency FPGA trading systems for global equity and futures markets to provide a competitive edge in market making.
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Distinguished Technologist - Memory/Storage Utilization & Data Placement Architect HpSpring, Texas, United States of America $190k–$274k3mo Define unified memory/storage hierarchy and data placement strategies for AI workloads, optimizing performance across DRAM, SSD, and cache layers.
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Physical Design Engineer CerebrasHeadquarters/Sunnyvale Office $230k–$230k3mo Design and analysis of 3D integrated products, combining traditional ASIC/SoC physical design with packaging, power, clock, and cooling analysis.
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Sr Principal Engineer AI/ML GlobalFoundriesSanta Clara, US $171k–$171k3mo Designing and leading the RTL development of an AI-enabled RISC-V CPU core, including vector extensions and matrix engines for physical AI applications.
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