Lead Engineer (IP Design & Microarchitecture)
Core
Designing low-power custom hardware accelerators and optimizing IP for Power, Performance, and Area (PPA) in Electronic Design Automation (EDA) tools.
Role type
Senior IC hardware accelerator designer (IP & Microarchitecture)
Builds
Custom hardware accelerators and design IPs for chip, board, and system design
Domain
Semiconductor EDA / Digital Logic Design
Deliverable
production ML models | product features | infrastructure
Required skills
RTL design (Verilog, SystemVerilog), digital microarchitecture, High-Level Synthesis (HLS), C/C++/Python/Bash coding, power/area/performance trade-off analysis, ASIC design cycle knowledge
Preferred skills
PhD in relevant field, experience breaking down DSP algorithms into RTL, full ASIC bring-up experience
Technologies
SystemC, C++, Python, Bash, HLS, Verilog, SystemVerilog
Responsibilities
Develop, test, maintain, and improve design IPs for optimal PPA; Implement functionality in SystemC/C++ meeting latency, throughput, area, and power goals; Perform power, area, and performance trade-off analyses; Leverage HLS to iterate and evaluate implementations; Drive coverage closure and meet sign-off criteria; Author detailed design documents articulating architectural choices
Seniority
Senior, hands-on IC
