ASIC Architect
Core
Designing and optimizing the micro-architecture of the world's largest AI chip to enable ultra-high-speed training and inference for AI workloads.
Role type
Senior ASIC Architect
Builds
Custom AI accelerators and chip architectures
Domain
Semiconductor hardware design / AI infrastructure
Deliverable
production ML models
Required skills
Computer architecture, performance analysis and modeling, PPA trade-offs, micro-architecture optimization, Python for performance modeling, kernel-level HW acceleration, workload profiling
Preferred skills
ML workload profiling, model network architecture understanding, micro-code optimization
Technologies
Python
Responsibilities
Translate high-level architecture specs to micro-architecture feature requirements, bring up new features in performance/power models, perform PPA trade-offs, profile workloads to identify bottlenecks, engage with SW teams for cluster-level application modeling, identify kernel-level HW acceleration opportunities
Seniority
Senior, hands-on IC