Director, Silicon Design Engineering
Core
Physical Design Timing Engineer ensuring optimal timing, power efficiency, and performance for Intel's next-generation System-on-Chip (SoC) products.
Role type
Senior IC Physical Design Timing Engineer
Builds
High-performance, power-optimized SoC designs
Domain
Semiconductor / Physical Design / Timing Analysis
Deliverable
production ML models | product features
Required skills
Static timing analysis, timing constraint generation, timing optimization, SoC clocking, timing budgeting, constraint adaptation, TCL scripting, digital design fundamentals, power and performance analysis
Preferred skills
Signal and power integrity analysis, advanced process nodes knowledge, industry-leading EDA tools expertise
Technologies
EDA tools, TCL
Responsibilities
Perform comprehensive timing analysis and optimization; Generate and validate timing constraints and address violations at chip and block levels; Conduct timing rollups; Develop methodologies for high-quality timing models; Define PVT conditions for precise timing analysis; Collaborate with clocking and full-chip designers to maintain clocking balance and optimize power delivery; Partner with architecture and logic design teams to validate clocking flows.
Seniority
Senior, hands-on IC
