Design Engineer
Core
Design and implement digital front-end RTL blocks, including high-speed datapaths for UCIe and optical front-end interfaces.
Role type
Senior IC RTL Design Engineer (Digital Front-End)
Builds
Digital logic blocks, datapath elements, and streaming adapters for optical transceivers and interconnects.
Domain
Semiconductor hardware design, optical communications, high-speed interfaces
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, micro-architecture design, pipelining, FSMs, FIFOs, clock-domain crossing, streaming/bus interfaces, lint/CDC/RDC discipline, power-aware design, timing closure, Python/Perl/TCL scripting
Preferred skills
UCIe/PCIe/CXL interface design, FEC/coding datapath, assertion-based verification, emulation/FPGA prototyping, low-power/UPF, DFT, optical transceiver/CPO background, advanced-node design
Technologies
SystemVerilog, UCIe, FPGA, Python, Perl, TCL, SVA
Responsibilities
Develop block-level micro-architecture and interface definitions; Design and implement front-end RTL blocks; Integrate IP and support parameterization; Write clean, lint-clean, CDC/RDC-clean RTL; Write block-level testbenches and assertions; Manage power and timing-aware design; Debug across simulation, emulation, and FPGA prototyping; Collaborate with architecture, DV, DFT, and backend teams
Seniority
Senior, hands-on IC
