Principal Digital Design Engineer
Core
Architect and design RTL in Verilog for mixed-signal integrated circuits, specifically digital sections of leading-edge memory data buffer chips for DDR5/DDR6.
Role type
Principal Digital Design Engineer (ASIC/IC)
Builds
Digital sections of memory data buffer chips for data centers (AI/cloud computing)
Domain
Semiconductor / Embedded Processing / Memory Interfaces
Deliverable
production ML models | product features | infrastructure
Required skills
Verilog RTL coding, ASIC design methodology, digital design implementation, logical synthesis, DFT insertion, static timing analysis, place and route constraints, formal verification, CDC/RDC checking, gate-level simulation, ECO implementation
Preferred skills
ATPG generation, ATE support, physical design
Technologies
Verilog, DDR5, DDR6, Synopsys/Cadence toolchains (implied by synthesis/STA/P&R), DFT tools
Responsibilities
Propose and architect RTL designs, oversee digital backend design (synthesis, STA, equivalence checking), create documentation for design/verification/test teams, mentor junior engineers
Seniority
Principal, hands-on IC design with mentorship
