Senior ASIC Timing Engineer
Core
Drive physical design and timing closure for high-frequency, low-power DPUs, SoCs, and chiplets at block, sub-chip, and full-chip levels.
Role type
Senior ASIC Timing Design Engineer
Builds
High-speed communication devices (DPUs, SoCs) for networking silicon
Domain
Semiconductor / ASIC Physical Design / Networking
Deliverable
production ML models | product features
Required skills
Static Timing Analysis (STA), timing constraints management, timing convergence, physical design optimization (placement, routing, cell sizing, buffering), logic synthesis, logical equivalence checking (LEC), Python/Tcl/Make scripting, EDA tool expertise (Synopsys PrimeTime, Cadence Tempus)
Preferred skills
DFT timing closure, deep sub-micron process variation modeling, flow/automation development, CPU/GPU/Network processor domain experience
Technologies
Synopsys PrimeTime, Cadence Tempus, Python, Tcl, Make
Responsibilities
Drive frontend and backend implementation from RTL to GDS2; analyze and optimize design constraints for performance, power, and area; fix timing paths through ECOs including crosstalk and noise analysis
Seniority
Senior, hands-on IC
