Sr. Physical Design Engineer
Core
Senior Physical Design Engineer owning full-chip and block-level physical implementation from RTL to GDSII for high-performance ASICs in advanced TSMC nodes (5nm/3nm).
Role type
Senior IC physical design engineer (advanced nodes)
Builds
High-performance ASICs using TSMC 5nm and 3nm processes
Domain
Semiconductor / Advanced Node ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
floorplanning, placement, CTS, routing, timing closure, power closure, area closure, signoff debugging, Tcl scripting, Python scripting, Perl scripting
Preferred skills
high-speed PHY implementation (SerDes, UCIe), EM/IR analysis, power grid optimization, congestion analysis, 2.5D/3D design (CoWoS, SoIC-X), high-frequency datapath support
Technologies
Synopsys ICC2, RedHawk SC, Cadence Innovus, Voltus, Siemens Calibre
Responsibilities
Own full-chip and block-level physical implementation including floorplanning, placement, CTS, routing, and physical verification; Collaborate with RTL and STA teams for timing, area, and power closure; Apply advanced techniques for multi-voltage/multi-frequency domains and congestion mitigation; Perform tapeout signoff activities including PV, EM/IR, ESD, and ejobview
Seniority
Senior, hands-on IC