Physical Design Technical Lead
Core
Own complex SOC and block-level implementation challenges end-to-end, from floorplan and power intent through final signoff, while shaping ML/AI-driven implementation flows.
Role type
Senior IC Physical Design Technical Lead
Builds
Advanced semiconductor SoC products for AI, cloud, networking, automotive, and edge computing markets
Domain
Semiconductor / Physical Design / EDA
Deliverable
production ML models | product features
Required skills
SOC floorplanning, place-and-route, static timing analysis (STA), power integrity analysis, physical verification, Tcl/Python scripting, ML/AI tool integration
Preferred skills
FPGA/structured-ASIC implementation, 3DIC/chiplet integration, high-speed I/O integration, EDA vendor beta programs
Technologies
Synopsys Fusion Compiler, Cadence Innovus, Synopsys PrimeTime, Ansys RedHawk, Cadence Voltus, Mentor Calibre, Python, Tcl
Responsibilities
Own floorplan architecture and power domain partitioning for large SoC designs; Drive block-level implementation through synthesis, place-and-route, CTS, and ECO closure; Achieve full signoff closure including STA, IR drop, and DRC/LVS; Champion integration of ML/AI-based optimization engines into production PnR flows; Mentor and technically guide a team of 3–8 physical design engineers
Seniority
Senior, hands-on IC with technical leadership
