DFx Engineer
Core
Architecting and implementing Design for Test (DFT) scan solutions for high-performance digital IP (CPU/GPU) and System-on-Chip (SoC) projects to ensure high test coverage and yield.
Role type
Senior IC Digital Design Engineer (DFT)
Builds
DFT scan architecture, RTL, timing constraints, and ATPG patterns for bleeding-edge process nodes.
Domain
Semiconductor / High-performance computing / Digital IP
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture design, RTL coding, Static Timing Analysis (STA), Physical Design knowledge, ATPG, silicon debugging, multi-voltage/multi-clock domain implementation, hierarchical DFT, streaming fabric
Preferred skills
Advanced DFT approaches, post-silicon debugging, creative problem solving
Technologies
RTL, LINT, ATPG, simulation tools
Responsibilities
Define DFT architecture balancing coverage and test-time; create detailed implementation specs; collaborate with SOC/RTL/STA/PD teams; implement DFT scan and benchmark coverage; drive DFX excellence and tool efficiency; resolve silicon issues and test escapes.
Seniority
Senior, hands-on IC
