Senior Physical Design Engineer
Core
Lead physical design and implementation of System-on-Chip (SoC) devices for networking markets, focusing on partition, chiplet, floorplan, power/clock distribution, and timing closure.
Role type
Senior IC physical design engineer (SoC/Networking)
Builds
High-speed communication chips (Networking Silicon)
Domain
Semiconductor / Networking / VLSI
Deliverable
production ML models | product features
Required skills
VLSI physical design implementation, RTL2GDS flow, place and route, timing closure, power and clock distribution, physical verification, RC extraction, CAD tool expertise (Synopsys/Cadence), analytical debugging
Preferred skills
ML/AI application in design flow, scripting (Python/Perl/Tcl/Make)
Technologies
Synopsys ICC2/DC/PT/STAR/ICV, Cadence Genus/Innovus/Tempus, 5nm/4nm/3nm nodes
Responsibilities
Lead physical design and implementation of SOC devices, establish physical design methodologies and flow automation, perform chip floorplan and assembly, conduct power and noise analysis, execute trial synthesis and place & route
Seniority
Senior, hands-on IC