High Speed Interface Protocols, Principal AE
Core
Architect high-speed interface solutions for customers using Cadence Serdes IP and showcase performance to win business opportunities.
Role type
Principal Applications Engineer (Technical Field Organization)
Builds
Serdes IP portfolio (PHY and controllers) for data centers, automobiles, and consumer devices
Domain
Semiconductor IP, High-Speed Interfaces (PCIe, CXL, Ethernet, USB)
Deliverable
client delivery
Required skills
High-speed interface protocols (PCIe, CXL, Ethernet, USB), PHY and controller architecture, pre-sales account management, technical presentation, application note writing
Preferred skills
Lab validation and demo setup, PHY/verification experience, AXI and PIPE protocols
Technologies
PCIe, CXL, UCIe, Ethernet, USB, MIPI, 224G, 112G, AXI, PIPE
Responsibilities
Technical presales and configuration of High-Speed Interface IP, Present IP portfolio to prospective customers, Serve as product expert in digital controller and PHY IPs, Work with Sales/Marketing/R&D to win opportunities, Demonstrate IP performance at industry events, Provide quick-turn technical support, Write application notes
Seniority
Principal, hands-on IC with leadership
