Silicon Physical Design Engineer
Core
Developing high-performance, power-efficient silicon layouts for next-generation AI superchips at leading-edge process nodes.
Role type
Senior IC silicon physical design engineer
Builds
Final chip layouts (GDSII) for AI compute chips
Domain
Semiconductor / AI hardware / Physical Design
Deliverable
production ML models | product features | infrastructure
Required skills
Floorplanning, Synthesis, Place and Route, Clock CTS, Timing Analysis, Physical Verification (DRC/LVS/ERC), Tcl scripting, Python scripting, debugging complex engineering problems
Preferred skills
2nm/3nm technology experience, CoWoS/UCIe packaging, high-speed interfaces (Ethernet/PCIe/HBM), power integrity optimization, team management
Technologies
7nm, 5nm, 3nm, 2nm, TSMC, EDA tools, Tcl, Python
Responsibilities
Deliver signoff-quality chip layouts using state-of-the-art EDA tools and in-house flows; enhance existing flows and tools/APIs; analyze and debug complex engineering problems; collaborate with RTL, verification, architecture, and packaging teams.
Seniority
Senior, hands-on IC