Director, Silicon Logical Design
Core
Lead and scale the Logical Design group to define micro-architecture and RTL for Graphcore's AI compute chips, ensuring world-class performance, power, area, and schedule.
Role type
Director, Silicon Logical Design
Builds
AI compute chips (micro-architecture and RTL)
Domain
Semiconductor / AI Compute
Deliverable
production ML models
Required skills
Digital logical design, micro-architecture, RTL development, SystemVerilog/VHDL, cross-functional leadership, project planning, design automation, timing closure, linting, synthesis, CDC/RDC, Python/Tcl scripting
Preferred skills
Processor/accelerator micro-architecture, high-speed serial interfaces, arithmetic pipeline design, floating-point datapaths, DFT, power integrity, silicon bring-up
Technologies
SystemVerilog, VHDL, Python, Tcl
Responsibilities
Define and execute strategic roadmap for Logical Design; Lead, grow and mentor high-performing RTL/micro-architecture design organisation; Provide technical oversight of micro-architecture specification and RTL development; Partner with Physical Design, Verification, DFT, Architecture and Program Management teams; Own delivery of high-quality, on-schedule RTL for multiple parallel silicon programs
Seniority
Director, hands-on IC leadership
