Senior Digital Engineer
Core
Design micro-architecture and front-end digital blocks for power management ASICs from concept to silicon.
Role type
Senior Digital Engineer (Power Management ASIC)
Builds
Power management ICs (PMICs) and mixed-signal integrated circuits
Domain
Semiconductor / Power Management / Mixed-Signal ICs
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Incorrect mapping in thought, correcting to: production hardware blocks / RTL designs)
Required skills
Verilog/System Verilog, Micro-architecture design, RTL coding, Logic Synthesis, Static Timing Analysis (STA), Clock Domain Crossing (CDC), Power estimation, Silicon debug, DFT strategy, I2C/PMBUS/SPI protocols, OTP/MTP/Efuse controller design
Preferred skills
Experience with mixed-signal ICs, Placement and Route sign-off, Innovative solution proposal
Technologies
Verilog, System Verilog, I2C, PMBUS, SPI, OTP, MTP, Efuse
Responsibilities
Develop digital functional blocks for power management ASICs, Lead optimized digital blocks design meeting functional and low power constraints, Handle Clock Domain Crossing across multiple clock domains, Perform silicon debugs and root cause analysis, Interface with Placement and Route team for digital hand-off, Author high-quality documentation for digital blocks
Seniority
Senior, hands-on IC
