Sr. Staff Hardware Design Engineer
Core
Designing the MSI Translation Engine (MTE) for RISC-V virtualization to ensure secure interrupt translation for high-performance computing and automotive applications.
Role type
Senior Staff Hardware Design Engineer (Memory Management & Virtualization)
Builds
Configurable IP for RISC-V SoCs, specifically the MTE component leveraging Chisel-based hardware generation.
Domain
Semiconductor chip design, RISC-V architecture, memory systems, virtualization
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL design (SystemVerilog/Verilog), Microarchitecture design, Memory system design (TLB, MSHR, caches), IOMMU mechanisms, RISC-V AIA/H-extension specs, AMBA protocols (AXI4), Chisel/Scala, Object-oriented programming
Preferred skills
RISC-V LTI protocol, PCIe stack (ATS/PRI), High-performance computing (HPC) experience, Automotive domain knowledge
Technologies
Chisel, Scala, SystemVerilog, Verilog, RISC-V, AXI4, PCIe
Responsibilities
Own the microarchitecture of the MSI Translation Engine, Develop RTL generators using Chisel, Design and optimize internal memory hierarchy, Collaborate with Core MMU and Architecture teams, Partner with DV teams for verification and Physical Design teams for timing closure
Seniority
Senior Staff, hands-on IC
