Logic Lead
Core
Architectural design and FPGA implementation of next-generation wireless protocol analyzers to capture, demodulate, and process high-speed RF signals.
Role type
Senior IC FPGA Logic Lead
Builds
High-performance protocol analyzers (e.g., Frontline X700) for testing Bluetooth, Wi-Fi 7, and IoT ecosystems
Domain
Test & Measurement Equipment / Wireless Protocols / FPGA Design
Deliverable
production ML models | product features | infrastructure
Required skills
FPGA architecture design, RTL design (SystemVerilog/Verilog/VHDL), high-speed bus interfaces, demodulator/decoder implementation, timing closure optimization, UVM verification, hardware debugging
Preferred skills
Commercial test equipment development, advanced timing closure techniques, Python/C/C++/MATLAB for hardware modeling
Technologies
AMD Xilinx UltraScale+/Versal, Intel Altera Stratix/Agilex, Vivado, SignalTap, PCIe, USB 3.0, DDR4/DDR5, Bluetooth LE/Classic
Responsibilities
Define FPGA architecture for protocol filtering and capture engines, Design RTL for hardware accelerators and memory controllers, Lead engineers through the complete FPGA development lifecycle, Mentor junior and mid-level digital design engineers, Build robust simulation and UVM testbench environments, Debug hardware issues on live FPGAs
Seniority
Senior, hands-on IC with leadership responsibilities
