ASIC Physical Design
1,421 open positions
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Product Engineer Siemens-EdaNew Cairo, EGY, Egypt $24k–$24k2mo Support the definition, promotion, and deployment of hardware-assisted acceleration using Veloce proFPGA CS prototyping solutions for semiconductor and systems customers.
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ASIC Design Engineer HpSingapore, South West, Singapore 2mo Design and verify digital ASIC components for inkjet and laserjet printing systems, supporting design implementation, silicon validation, and system integration.
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Principal Interconnect Design Engineer SifiveSanta Clara, CA, US $231k–$231k2mo Designing industry-leading CPU and interconnect IP, specifically TileLink interconnects and cache controllers, to drive RISC-V adoption in SOC designs.
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E-Core (Atom) CPU Layout Design Engineer IntelMalaysia, Penang 2mo Design physical implementation of memory compilers, custom IP blocks, and layout partitions for Intel Atom microprocessors.
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Chip Design Engineer
AmazonTel Aviv-Yafo, Tel Aviv, Israel
2mo
Designing and delivering high-end custom silicon for AWS cloud infrastructure, specifically the Nitro platform.
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R&D Engineer IC Design 4 BroadcomUSA-CA San Jose Innovation Drive $122k–$122k2mo Front-end design and verification of design blocks for ASIC cores, translating system requirements into logic and ensuring timing closure.
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AI CPU Design Engineer GlobalFoundriesIND - Karnataka - Bengaluru - Central, IN 2mo Design and verification of AI-enabled RISC-V CPU cores, including vector extensions and matrix engines, focusing on performance, power, and area optimization.
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Senior ASIC Hardware Design Engineer NVIDIAUS, MA, Westford $136k–$136k2mo Design and implement next-generation NVLink protocol and GPU subsystem logic for high-speed chip-to-chip communication and high-performance, low-power GPU and interconnect subsystems.
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SoC Architect ArmMultiple locations $309k–$309k2mo Architecting and designing high-volume, sophisticated System-on-Chip (SoC) platforms on groundbreaking nodes across mobile, automotive, datacenter, networking, and IoT market segments.
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ASIC Design Engineer HpeBengaluru, Karnātaka, India 2mo Architecting and designing high-performance blocks for advanced networking ASICs to deliver maximum throughput with minimum power.
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Senior FPGA Mixed Signal Engineer AnalogdevicesFrance, Sophia-Antipolis 2mo Design and develop FPGA-based solutions for mixed-signal systems and evaluation platforms, focusing on Xilinx Zynq devices.
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Chip Design Engineer, Graviton Team
AmazonTel Aviv-Yafo, Tel Aviv, Israel
2mo
Design and develop semiconductor processors (SoC) for cloud infrastructure, driving architecture from definition through tape-out.
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Senior FPGA Design Engineer AnellophotonicsSanta Clara, CA 2mo Lead FPGA-based hardware development for integrated photonic system-on-chip and AI technology for next-generation navigation in GPS-Denied environments.
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Principal ASIC Physical Design Engineer K2spacecorporationSeattle $190k–$190k2mo Lead the implementation of complex SoCs for next-generation satellite and space systems, owning the full physical design flow from RTL handoff to GDSII.
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Hardware Design Engineer, Ethernet Switching Arista-NetworksBengaluru, KA, in 2mo Designing high-speed Ethernet switching hardware for AI clusters, hyperscale datacenters, and enterprise campuses.
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AE Group Director CadenceGYEONGGI-DO (Seoul) 2mo Lead digital IC implementation projects including floorplan, power-plan, placement, CTS, routing, SI & STA signoff.
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EE 硬體研發工程師 - Server (ACG/ 林口園區) AdvanTechLinkou 2mo Design and validate server system hardware for x86 platforms, focusing on high-speed interfaces and power management.
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Senior Manager, ASIC AI PDT Lead MicronHyderabad - Phoenix Aquila, India 2mo Lead AI initiatives across ASIC/SoC development programs, driving adoption, establishing metrics frameworks, and coordinating deliverables to measure AI usage and productivity improvements.
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<GPU> GPU Architect Technical Manager/Senior Engineer MediaTekHsinChu 2mo Optimize GPU performance, area, and power for graphics and compute workloads through memory sub-system design, low-power strategies, and system modeling.
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ASIC Design Engineer, STA CiscoSan Jose, California, US $153k–$153k2mo Develop methodologies, guidelines, and checklists for static timing analysis (STA) flow, resolve design and flow issues, and ensure convergence between PNR, Spice, and STA for web scale and service provider network silicon.
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Senior FPGA Engineer (Algo) DrwengChicago $150k–$150k2mo Architect and implement low-latency, high-throughput FPGA applications from scratch for a diversified trading firm's trading teams.
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Physical Design Engineer AccentureBengaluru 3mo Translate logical circuit designs into physical layouts, optimizing for area, power, and timing while ensuring manufacturing constraints are met.
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Digital IC Design Engineer Texas InstrumentsDallas, TX, United States 3mo Design and verify digital logic for next-generation power management and analog ICs serving industrial, automotive, and consumer applications.
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Hardware Design Engineer PurestorageOffice - Taipei (Taiwan) 3mo Architect and launch next-generation high-performance solid-state storage solutions from concept to global mass production, focusing on high-speed hardware interfaces to reduce TCO and energy consumption.
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Principal Engineer, Automated Derivatives Renesas-ElectronicsRemote 3mo Lead end-to-end delivery of derivative System-on-Chips (SoCs) by building an AI-augmented 'Silicon Factory' that uses machine learning to bridge architectural intent and GDSII, focusing on ultra-fast turnaround times.
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Hardware Engineer ImcChicago $200k–$200k3mo Design and verify custom ASICs for low-latency trading infrastructure, collaborating with software and research teams to solve complex hardware challenges.
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Principal System Engineer NxpCaen, FR 3mo Lead architectural definition, design, and implementation of complex embedded systems for next-generation semiconductor products.
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ASIC / Digital Design Director of Engineering ON SemiconductorBangalore, Karnataka, India 3mo Lead development of next-generation Automotive Networking solutions including SerDes, Ethernet, and high-speed communication SoCs.
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