Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Core
Developing cutting-edge next-generation silicon for deployment in space and ground infrastructures to enable global connectivity via the Starlink network.
Role type
Senior IC SOC/ASIC Physical Design Engineer
Builds
Next-generation silicon chips for Starlink satellites and ground receivers
Domain
Aerospace / Semiconductor Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ASIC/SOC RTL2GDSII physical design flow, EDA tools (synthesis, place & route, signoff), deep sub-micron FinFET/CMOS physics, scripting (Python, TCL, Perl, Bash), static timing analysis (STA), physical verification, electromigration analysis, power/ground grid generation
Preferred skills
Analog circuit physical design, DFT/Scan/MBIST/LBIST knowledge, RTL/design tradeoff analysis, automation script development
Technologies
Synopsys/Cadence EDA suites, Python, TCL, Perl, Bash, Makefile
Responsibilities
Perform partition synthesis and physical implementation (floorplanning, place and route, signoff checks), develop/improve physical design methodologies and automation scripts, collaborate on architectural feasibility and timing/power/area targets, resolve design/timing/congestion issues, debug signoff closure issues in STA and physical verification
Seniority
Senior, hands-on IC